JVET-P0454 Non-CE8: Constraints on IBC reference block locations [X. Xu, X. Li, S. Liu (Tencent)]

In this contribution, a constraint is imposed on the reference block location for IBC, such that all samples of the reference block should be in the same 64x64 grid aligned region in the current picture.

It is reported that the proposed modification avoids an encoder to generate some of the bitstreams that contain samples from disconnected areas in the decoded part of current picture, therefore reduce the efforts for conformance testing.

Simulation results reportedly show that the BD rate changes are as follows:

For method 1:

• For class F, 0.43%/0.35%/0.41% for AI/RA/LB configurations.
• For class TGM, 1.22%/0.86%/0.70% AI/RA/LB configurations.

For method 2:

• For class F, 0.17%/0.10%/0.18% for AI/RA/LB configurations.
• For class TGM, 0.42%/0.31%/0.16% AI/RA/LB configurations.

The argument of the proposal is that the current spec. enforces decoders to implement the storage following the VPDU concept, otherwise they would need to implement additional steps for the wraparound.

It is agreed that method 2 (imposing additional checks in the decoder) should not be used.

It is suggested by several experts that the bitstream constraint would simplify decoders that would not implement following precisely the VPDU concept. It is however not clear if the proposed text covers all corner cases. There is some concern that it might destabilize the specification, where it took several meeting cycles to get to a solution that guarantees operation of IBC with limited local memory.

It is also asked if...

JVET-P0733 Crosscheck of JVET-P0454 on constraints on IBC reference block locations [X. Xiu (Kwai Inc.)]

JVET-P2025 Description of Core Experiment 5 (CE5): Cross-component adaptive loop filtering [C.-Y. Chen, A. Segall]

See track A notes under JVET-P1033 about what to test.

Future meeting plans, expressions of thanks, and closing of the meeting

Future meeting plans were established according to the following guidelines:

• Meeting under ITU-T SG 16 auspices when it meets (ordinarily starting meetings on the Tuesday of the first week and closing it on the Wednesday of the second week of the SG 16 meeting – a total of 9 meeting days), and
• Otherwise meeting under ISO/IEC JTC 1/SC 29/WG 11 auspices when it meets (ordinarily starting meetings on the Tuesday prior to such meetings and closing it at lunchtime on the last day of the WG 11 meeting – a total of 9.5 meeting days).

In cases where an exceptionally high workload is expected for a meeting, an earlier starting date may be defined. For the upcoming meeting in October 2019, the SG16 parent-level meeting dates had been shifted after the JVET and MPEG meeting plans were established, which has caused an additional adjustment in the JVET dates.

Some specific future meeting plans (to be confirmed) were established as follows:

• Tue. 7 – Fri. 17 January 2020, 17^th meeting under WG 11 auspices in Brussels, BE.
• Wed. 15 – Fri. 24 April 2020, 18^th meeting under WG 11 auspices in Alpbach, AT.
• Tue. 23 June – Wed. 1 July 2020, 19^th meeting under ITU-T auspices in Geneva, CH.
• Wed. 7 – Fri. 16 October 2020, 20^th meeting under WG 11 auspices in Rennes, FR.

The agreed document deadline for the 17^thJVET meeting was planned to be Tuesday 31 December...