JVET-P0454 Non-CE8: Constraints on IBC reference block locations [X. Xu, X. Li, S. Liu (Tencent)]
In this contribution, a constraint is imposed on the reference block location for IBC, such that all samples of the reference block should be in the same 64x64 grid aligned region in the current picture.
It is reported that the proposed modification avoids an encoder to generate some of the bitstreams that contain samples from disconnected areas in the decoded part of current picture, therefore reduce the efforts for conformance testing.
Simulation results reportedly show that the BD rate changes are as follows:
For method 1:
- For class F, 0.43%/0.35%/0.41% for AI/RA/LB configurations.
- For class TGM, 1.22%/0.86%/0.70% AI/RA/LB configurations.
For method 2:
- For class F, 0.17%/0.10%/0.18% for AI/RA/LB configurations.
- For class TGM, 0.42%/0.31%/0.16% AI/RA/LB configurations.
The argument of the proposal is that the current spec. enforces decoders to implement the storage following the VPDU concept, otherwise they would need to implement additional steps for the wraparound.
It is agreed that method 2 (imposing additional checks in the decoder) should not be used.
It is suggested by several experts that the bitstream constraint would simplify decoders that would not implement following precisely the VPDU concept. It is however not clear if the proposed text covers all corner cases. There is some concern that it might destabilize the specification, where it took several meeting cycles to get to a solution that guarantees operation of IBC with limited local memory.
It is also asked if the wraparound and the VPDU concept would be needed any more.
It is also mentioned that the loss might be larger with other CTU sizes.
See further notes under JVET-P1018.