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16th Meeting: Geneva, October 2019 2019-09-27 14:11
Level restrictions on maximum tile width for line buffer reduction
Authors: M. Ikeda Sony Y. Yagasaki Sony Teruhiko Suzuki Sony Masaru Ikeda
Abstract
This document proposes to have level constraints on the maximum tile size to reduce line buffer. It is proposed that the constraint on maximum tile width is introduced and the value is set depending on maximum picture size. It can provide hardware decoder implementations with the reduction of the amount of line buffer that is required for in-loop filters.
Meeting Notes
JVET-P0295 Level restrictions on maximum tile width for line buffer reduction [M. Ikeda, Y. Yagasaki, T. Suzuki (Sony)]
PATENTS:
US20080063078A1 0.34 2008-03-13 US20210092415A1 0.32 2021-03-25 CN104041034B 0.30 2018-10-16 CN105227952B 0.28 2018-10-19 WO2016147836A1 0.26 2016-09-22 TW202106014A 0.24 2021-02-01 CN102428699A 0.22 2012-04-25 CN102428698A 0.20 2012-04-25
ARCHIVE v2 :
JVET-P0295-v2.docx JVET-P0295-v2_clean.docx
Decisions
JVET-P0295 Level restrictions on maximum tile width for line buffer reduction [M. Ikeda, Y. Yagasaki, T. Suzuki (Sony)]
Citation