Back to Search Document details
13th Meeting: Marrakech, January 2019 2019-01-03 04:24
CE6: Fast DST-7/DCT-8 with dual implementation support (Test 6.2.3)
Authors: Xin Zhao Tencent Xinwei Li Tencent Y. Luo Tencent Shan Liu Tencent
Abstract
This contribution reports the test results of CE6-2.3 on a fast DST-7/DCT-8 method with dual implementation support, i.e., identical results between full matrix multiplication and fast method. Compared to full matrix multiplication, the proposed method reportedly reduces the multiplication operation counts by 50% and 39% for 16- and 32-point DST-7/DCT-8, respectively. It is reportedly shown that, on top of VTM-3.0, average 0.01%, -0.01% and 0.00% luma BD-Rate is achieved under All Intra (AI), Random Access (RA) and Low Delay B (LDB) configurations, respectively, and an average of 4% and 9% overall run-time can be saved for encoding and decoding under AI test condition, respectively.
Meeting Notes
JVET-M0497 CE6: Fast DST-7/DCT-8 with dual implementation support (Test 6.2.3) [X. Zhao, X. Li, Y. Luo, S. Liu (Tencent)]
References:
JVET-K0291 JVET-K1001 JVET-L0286 JVET-L1001 JVET-L1010 JVET-L1026
Cited:
JVET-M0026 JVET-M1001 JVET-N0002 JVET-N0003 JVET-N0013 JVET-N0075 JVET-N0076 JVET-N0077 JVET-N0078 JVET-N0079 JVET-N0081 JVET-N0085 JVET-N0086 JVET-N0088 JVET-N0097 JVET-N0107 JVET-N0108 JVET-N0115 JVET-N0116 JVET-N0119 more than 20
PATENTS:
US8885701B2 0.71 2014-11-11 US12549768B2 0.70 2026-02-10 JP2005535055A 0.32 2005-11-17 US12088805B2 0.32 2024-09-10 US10986339B2 0.30 2021-04-20 US12256092B2 0.28 2025-03-18 US12238318B2 0.26 2025-02-25 US11758157B2 0.22 2023-09-12
ARCHIVE v1 :
JVET-M0497-CE6-2-3a.XLSM JVET-M0497-CE6-2-3a_LowQP.XLSM JVET-M0497.docx
Decisions
JVET-M0497 CE6: Fast DST-7/DCT-8 with dual implementation support (Test 6.2.3) [X. Zhao, X. Li, Y. Luo, S. Liu (Tencent)]
Citation