JVET-L0394 On Conflicting Use of Tiles [S. Wenger (Tencent)]
Proposed are a) a tile hierarchy intended to reconcile possibly contradicting requirements imposed on the tile layout by application and parallelization needs, and b) a set of flags that, for each hierarchy level in the tile hierarchy, specify which prediction mechanisms are broken across tile boundaries.
The tile layout that would be motivated by a desire for parallelization is different from what would be desired for other reasons.
The contribution suggests considering having different types of control over the properties of tiles and considering having flags to control over what sorts of prediction mechanisms are broken at tile boundaries.
It was commented that the entry points into the decoding process in HEVC are coupled with the data layout and the locations where the prediction operations are broken.