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CE9-related: Simplification of Decoder Side Motion Vector Derivation
Abstract
This contribution presents two modifications on Decoder Side Motion Vector Derivation (DMVR) in the benchmark set (BMS): 1) DMVR for 4x4 blocks is disabled; 2) Partial Sum of Absolute Differences (SAD) is calculated instead of full SAD. Simulation results reportedly show 0.xx% BD-rate increase under BMS Random Access (RA) configurations.
JVET-K0105 CE9-related: Simplification of Decoder Side Motion Vector Derivation [H. Liu, L. Zhang, K. Zhang, Y. Wang, P. Zhao, D. Hong (Bytedance)]
This contribution presents two modifications on Decoder Side Motion Vector Derivation (DMVR) in the benchmark set (BMS): 1) DMVR for 4x4 blocks is disabled; 2) Partial Sum of Absolute Differences (SAD) is calculated instead of full SAD. Simulation results reportedly show 0.05%/0.07% BD-rate increase for BMS-1.0/VTM-1.0 under BMS Random Access (RA) configurations.
Two aspects:
- Disallow DMVR for 4x4 blocks (having 4x8/8x4 as smallest block size decreases worst case memory bandwidth increase from 140% to 136%)
- Perform SAD calculation on every second row
Further study in a CE was requested, but also restriction to even larger block sizes should be considered.
It was noted that the results show an encoding time increase, but the measurement is inaccurate according to the proponents.
References:
PATENTS:
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Decisions
noted
It was noted that the results show an encoding time increase, but the measurement is inaccurate according to the proponents.
Citation