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17th Meeting: Brussels, January 2020 2020-01-06 20:35
AHG12: Constraints on tile signaling
Authors: Xiang Ma Huawei Hyeong-Gyun Yang Huawei
Abstract
In the current VVC draft specification, there is no constraints on the value of tile_column_width_minus1[ i ] and tile_row_height_minus1[ i ], which are used to signal the width and height of the i-th tile column in units of CTBs, respectively. Meanwhile, the constraint on the tile_idx_delta[ i ], which used to signal the difference in tile index between the i-th rectangular slice and the ( i + 1 )-th rectangular slice, is not complete. It is proposed to add some constrains on value of these syntaxes to make the signaled values of these syntaxes valid.
Meeting Notes
JVET-Q0359 AHG12: Constraints on tile signalling [X. Ma, H. Yang (Huawei)]
Cited:
JVET-Q0012 JVET-Q0586 JVET-Q2001 JVET-R0002 JVET-R0003 JVET-R0060 JVET-R0062 JVET-R0081 JVET-R0082 JVET-R0141 JVET-R0142 JVET-R0208 JVET-R0218 JVET-R0219 JVET-R0221 JVET-R0305 JVET-R0350 JVET-R0370 JVET-R0392 JVET-R0481 more than 20
PATENTS:
20250267290 0.34 WO/2021/061285 0.33 20210329265 0.32 WO/2020/140063 0.31 20250047847 0.30 20230344999 0.28 20210329236 0.27 WO/2020/142483 0.26
ARCHIVE v3 :
JVET-Q0359_r2.docx
Decisions
JVET-Q0359 AHG12: Constraints on tile signalling [X. Ma, H. Yang (Huawei)]
Citation