This contribution provides a proposal of a bit-width reduction method of a multiplier in both CCLM derivation and prediction process. In the VTM3.0 implementation, a parameter in the linear prediction model has 19 bit including sign bit for the derivation process. For the prediction stage, a multiplier requires 29 bit due to the 19 bit parameter and 10 bit signal. The bit-width of multiplier in the CCLM prediction is wider than that of the motion compensation stage such as 21 bit. In this contribution, bit-width reduction of multiplier is presented which consists of four parts. Firstly, a range of chroma difference is restricted into +/− 256 for 10 bit chroma signal. Secondly, precision of a derivation table is reduced from 16 bit to 8 bit with a small value modification. Thirdly, a range of prediction parameter is restricted into +/− 8.0. Lastly, prediction parameter representation is changed from the 19 bit fixed-point number to the floating-point number with 7 bit fraction. A simulation result by the proposed method shows 0.01% / 0.03% / -0.01% for Y/U/V at the AI condition.